The IEEE Journal of Solid-State Circuits, Volume SC-17, Number 6, December 1982, includes a paper by Paul R. Gray and Robert R. Meyer entitled "MOS Operational Amplifier Design--A Tutorial Overview". The paper discusses design and implementation considerations of complimentary metal oxide semiconductor (CMOS) operational amplifiers (e.g. Gray paper, FIG. 2b) and their use with output buffer stages (e.g. Gray paper, FIG. 25) for driving large capacitive or resistive loads. It is generally desirable that the buffer stage exhibit both a source (i.e. providing positive conventional current to the load) capability and a sink (i.e. negative conventional current to the load) capability. The term buffer amplifier will be used herein to refer to a circuit combination of an amplifier means, e.g. an operational amplifier, together with a buffer output stage.
Although the theoretical circuit design of buffer amplifiers is relatively straight forward, physical constraints of available CMOS technologies raise considerable problems in the implementation of such designs. For example only, a major drawback of the buffer stage depicted in FIG. 25 of the Gray paper is the high threshold of the output transistors which limits the output voltage swing. The high threshold is attributable, in part, to the typical characteristics of available CMOS technology implementations. The so called "P-well" process has the back gates of all P-channel devices connected mandatorially to the positive supply voltage. The "N-well" process has the back gates of all the N-channel devices connected to the negative supply voltage. The result is that on a "P-well" process, each P-channel output device has a high threshold when operating near the negative supply and therefore cannot provide good output swing. Similar remarks apply to the N-channel device on an "N-well" process when operated near the positive supply. This is due primarily to the "body effect" phenomenon which raises thresholds in the presence of significant back-gate reverse bias.